1. Field of the Invention
The present invention relates to a pattern inspection apparatus and method, and more particularly to an apparatus and a method for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data.
2. Description of the Related Art
For the pattern inspection of a wafer in a fabricating process of semiconductor integrated circuit or the pattern inspection of a photomask for pattern formation of a wafer, an optical pattern inspection apparatus that uses the die-to-die comparison method has been used. In the die-to-die comparison method, a defect is detected by comparing an image obtained from a die to-be-inspected and an image obtained from the equivalent position of a die adjacent to the die to-be-inspected. In this case, the die means a semiconductor device.
On the other hand, for the inspection of a photomask (reticle) having no adjacent die, the die-to-database comparison method has been used. In the die-to-database comparison method, mask data is converted into an image. Then the image is used for a substitution of the image of the adjacent die used in the die-to-die comparison method, and inspection is performed in the same manner as the above. Here, the mask data is data obtained by applying photomask correction to design data. The technology concerned is disclosed, for example, in U.S. Pat. No. 5,563,702, “Automated photomask inspection apparatus and method.”
However, by using the die-to-database comparison method for wafer inspection, corner roundness of a pattern formed on a wafer is likely to be detected as a defect. In the inspection of a photomask, a pretreatment, which adds corner roundness to the image converted from the mask data by applying a smoothing filter, prevents the corner roundness of the pattern from being detected as the defect. However, in the inspection of a wafer, because the corner roundness added by the pretreatment may be different from corner roundness of each pattern actually formed on the wafer, the pretreatment may not perfectly prevent the corner roundness of the pattern from being detected as the defect. Therefore, an allowable pattern deformation quantity should be set in order to ignore the above difference. As a result, a problem in which a fine defect existing in a place except a corner cannot be detected has happened.
The above problem is not severe for the die-to-database comparison photomask inspection, because the photomask should correspond to the mask data as much as possible. Therefore, currently, the die-to-database comparison photomask inspection has been put into practical use. However, the above problem is severe for the die-to-database comparison wafer inspection, because a pattern formed on the wafer is allowed to be deformed as long as an electrical property is guaranteed. This allowable pattern deformation quantity is considerably large. Actually, pattern deformation occurs due to a difference in stepper exposure conditions, or the like. Therefore, the die-to-database comparison wafer inspection has not been put into practical use.
From a viewpoint of problems in semiconductor integrated circuit fabrication, repeated defects (systematic defects) are more important issue than a random defect caused by a particle or the like. The repeated defects are defined as defects that occur repeatedly over all dies on a wafer caused by photomask failure, or the like. Because the repeated defects occur in a die to-be-inspected and in adjacent dies that are to be compared with the die to-be-inspected, the die-to-die comparison wafer inspection cannot detect the repeated defects. Therefore, the die-to-database comparison wafer inspection has been demanded.
Although the die-to-die comparison wafer inspection has not been put into practical use because of calculation cost or the like, there have been proposed inspection methods in which design data and a wafer image are used. These inspection methods are disclosed in, for example, a literature: “Automatic failure part tracing method of a logic LSI using an electron beam tester,” NEC Technical Report, vol. 50, No. 6, 1997. In this literature, the following methods are disclosed: a method in which projections of wiring edges on the X- and Y-axes are used; a method in which wiring corners are focused on; and a method in which a genetic algorithm is applied. Moreover, as a method used in this literature, a matching method in which after edges are approximated by straight lines, closed areas are extracted, and the closed areas are used for matching is described. However, these methods fail to realize an inspection speed that is usable in high-speed inspection, and fail to perform matching while detecting a pattern deformation quantity.
Further, currently, the automatic defect classification (ADC) method in which an image of a die having a defect is used has been used. However, the method cannot classify whether the defect is a killer defect or not, because the method cannot recognize which part of a circuit the defect destroys.
Moreover, a position of a defect detected by the die-to-die comparison inspection has an error caused by precision of a stage and an optical system of an inspection apparatus, and such error is approximately ten or more times larger than a line width of a pattern to-be-inspected. Due to the error, even if a defect position is related with design data, relationship between the defect position and the design data cannot be recognized.
Currently, a line width of semiconductor integrated circuits is far shorter than wavelength used in a lithography process. In the lithography process, a method of adding an OPC (Optical Proximity Correction) pattern has been used. In the method, by using a photomask fabricated by mask data that is generated by adding an OPC pattern to design data, a pattern formed on a wafer fabricated by the photomask can be consistent with the design data as much as possible. Adding an OPC pattern is one of the most important techniques for photomask correction.
If the OPC pattern does not effectively correct a pattern formed on a wafer, repeated defects occur. However, the die-to-die comparison wafer inspection cannot detect the repeated defects. In order to solve this problem, it is necessary to provide a method in which a pattern formed on the wafer is inspected based on design data in consideration of an allowable pattern deformation quantity.
In addition, in a multi-product/small-volume fabricating process, e.g. a system-on-a-chip (SoC) fabricating process, a short delivery time is required. In the fabricating process, when repeated defects are detected in electric inspection as a final inspection, a short delivery time cannot be achieved. In order to solve this problem, it is necessary to provide an inspection method that inspects a difference between a pattern formed on a wafer and design data for each lithography process. In the inspection method, it is necessary for an allowable pattern deformation quantity that does not affect an electrical property to be set, and a deformation quantity that exceeds the allowable pattern deformation quantity should be detected.
Further, a lithography simulator inspects a simulation pattern, which is obtained from mask data to which an OPC pattern is added, by comparing the simulation pattern with design data in order to evaluate the OPC pattern. Although the entire device can be verified by the lithography simulator, the simulation pattern cannot be necessarily the same as an actual pattern. Moreover, a defect except for a defect caused by the OPC pattern cannot be detected by the lithography simulator. A random defect existing on a photomask, a stepper aberration, or the like is an example of such defect.
Moreover, for verifying the simulation, it is necessary to provide a method in which a simulation pattern outputted from the lithography simulator is verified with an image of a pattern actually formed on a wafer. Moreover, it becomes increasingly important to improve the technology for circuit design by setting an allowable pattern deformation quantity to design data precisely and in detail.
A CD-SEM (Critical Dimension Scanning Electron Microscope) has been used for controlling a line width in a fabricating process of semiconductor integrated circuits. The CD-SEM automatically measures a line width of a line-shaped pattern in a specified position using a line profile. Several positions in several shots on several pieces of wafers for each lot are measured in order to control stepper exposure condition by using the CD-SEM.
As control items in a fabricating process of semiconductor integrated circuits, end shrinkage of a wiring, a position of an isolated pattern, and the like are also important besides the line width, but the automatic measuring function of the CD-SEM allows only one-dimensional measurement. Specifically, the CD-SEM can measure only a length such as a line width. Therefore, those two-dimensional shapes are inspected by an operator manually using an image acquired from the CD-SEM or other microscopes.
The isolated pattern includes a hole pattern or an island pattern. The island pattern may be a negative pattern of the hole pattern. The hole pattern includes a contact hole/via hole or a test pattern.
Generally, an OPC pattern plays an important role not only to guarantee a gate line width, but also to form shapes of a corner and an isolated pattern. Furthermore, because of improvement of a processor frequency, control of a shape of an end of a gate pattern, which is called an end-cap, or a base of a gate pattern, which is called a field extension, also becomes important in addition to the gate line width.
The above inspections of two-dimensional patterns are essential both in sampling inspection in a fabricating process, and in an R&D fabricating process. Especially, in the R&D fabricating process, it is necessary to inspect all patterns formed on a wafer. However, currently, the control of the two-dimensional shape is performed by a human work, and is not perfectly performed. In order to solve this problem, automated die-to-database comparison wafer inspection is required.
As concrete subjects for automatization, the following subjects are enumerated:
1. In order to detect repeated defects in each semiconductor device, it is practically difficult to check whether there are defects at the same location by checking huge defect information.
2. An end except for an end-cap and an end of a wiring pattern to be connected to a contact hole/via hole may not be corrected by an OPC pattern correctly. Even if the end is shrunken by more than an allowable pattern deformation quantity for an end-cap or an end of a wiring pattern to be connected to a contact hole/via hole, it is not necessary to recognize the shrunken end as a defect.
3. Conventionally, an overlay error is controlled by measuring limited areas in a semiconductor device. Therefore, the overlay error caused locally by a stepper aberration or the like cannot be controlled.
4. The conventional die-to-die comparison method is performed by comparing corresponding two images. In this method, because the corresponding two images to be compared have different relationship between a pattern to-be-inspected and pixel boundaries, it is necessary for luminance values of pixels to be interpolated so that the two images have the same relationship between the pattern to-be-inspected and the pixel boundaries. A problem in which inspection accuracy becomes low by the interpolation arises.
5. A contour obtained from the second edges can be used for input data of a lithography simulator or the like. In this case, it is necessary to input the contour indirectly, because lithography simulator processing is slower than contour output processing.
6. The optimal allowable pattern deformation quantity depends on a desirable electrical property. Therefore, it is necessary to provide a method of obtaining an optimal allowable pattern deformation quantity by inspecting a standard specimen, which is judged as a semiconductor device having good quality.
7. For improving quality of semiconductor device, it is necessary for all gate widths in a semiconductor device to be measured, the measured gate widths are classified based on gate lengths, the minimum distances to the nearest pattern, or the like, and the gate widths are analyzed. However, by using a conventional CD-SEM, only a limited number of gate widths in a semiconductor device can be measured and classified practically.
8. As a method of improving quality of an image of a pattern to-be-inspected, the image-accumulation method is well known. However, in the case where images of a pattern to-be-inspected on a specimen liable to cause the electrification phenomenon are acquired successively, a sharp accumulated image cannot be obtained by accumulating the acquired images simply, because the acquired images are distorted gradually.
9. In the case of large distortion quantities of the image of the pattern to-be-inspected, vectors between a reference pattern and edges of an image of a pattern to-be-inspected that exceed an allowable deformation quantity cannot be obtained, and therefore the distortion quantities of the image of the pattern to-be-inspected may not necessarily be obtained accurately.
10. In order to improve inspection speed, a method in which an image of a pattern to-be-inspected is acquired by using a continuously moving stage and a line-sensor is used. However, by using the method, an image of a pattern to-be-inspected cannot be acquired by performing interlace scan or image-accumulation scan. The image accumulation scan means scan, in which the same scanning line is scanned two or more times in order to acquire an accumulated image.
11. In the case where the conventional automatic focus adjustment used in a CD-SEM is used for the image generation device with a large field of view, it takes a long time to acquire images of a pattern to-be-inspected. In addition, because a large area is scanned repeatedly, a specimen is drastically damaged by an electron beam scanning.
12. In order to measure an FEM wafer, conventionally, several points in all semiconductor devices on a wafer are measured by a CD-SEM. The points to be measured are points suitable for measuring line widths of line parts of patterns to-be-inspected. However, a tendency for pattern deformation quantities with regard to line widths of line parts of patterns to-be-inspected, and a tendency for pattern deformation quantities with regard to space widths of the line parts or a tendency for edge placement errors of ends of the patterns to-be-inspected may be different. In such case, if a process window is obtained from the results of measurement with regard to the line widths of the line parts of the patterns to-be-inspected, a semiconductor fabricated by exposure under conditions in the process window may have a defect.
13. In order to write a photomask pattern by using an electron beam mask writer or a laser beam mask writer, there is a method in which a shaped beam such as a rectangle beam is used for exposure. The shaped beam is deformed and exposed, so that a photomask pattern may be deformed more than an allowable pattern deformation quantity. Conventionally, the shaped beam is controlled by exposing a test pattern before writing a photomask pattern of a product. However, there has not been a method in which the shaped beam, which is deformed during the exposure of the photomask pattern of the product, is controlled.